GD25Q40CPFG datasheet(32/64 Pages) GIGADEVICE

Part #	GD25Q40CPFG

Description	3.3V Uniform Sector Dual and Quad Serial Flash

PDF	64 Pages

Scroll/Zoom	100%

Manufacturer	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Direct Link	http://www.gigadevice.com/

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32 / 64 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q40C

Figure 29. High Performance Mode Sequence Diagram

7.25.

Continuous Read Mode Reset (CRMR) (FFH)

The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce

command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the

BBH/EBH/E7H command code.

Because the GD25Q40C

has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25Q40C

will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous

Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in

Figure28.

Figure 30. Continuous Read Mode Reset Sequence Diagram

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

FFH

Mode Bit Reset for Quad/Dual I/O

Don`t Care

Command

A3H

CS#

SCLK

29 30 31

MSB

3 Dummy Bytes

23 22

High Performance Mode

HPM

GD25Q40CPFG Datasheet(PDF) 32 Page - GigaDevice Semiconductor (Beijing) Inc.