GD25WD20CSFG datasheet(19/49 Pages) GIGADEVICE

19 / 49 page

Uniform Sector

Standard and Dual Serial Flash

GD25WD40C/20C

The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address

bytes and at least one data byte on SI.

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the

current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-

A0) are all zero). CS# must be driven low for the entire duration of the sequence.

The Page Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI

 at least 1 byte data on SI  CS# goes high. The command sequence is shown in Figure8.

If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are

guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are

correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS#

must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command

is not executed.

As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page

Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Page Program (PP) command is not executed when it is applied to a page protected by the Block Protect (BP2,

BP1, BP0).

Figure8. Page Program Sequence Diagram

7.9. Sector Erase (SE) (20H)

The Sector Erase (SE) command is for erasing the all data of the specific sector. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered

by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid

address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.

The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-byte address on SI 

CS# goes high. The command sequence is shown in Figure9. CS# must be driven high after the eighth bit of the last address

byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the

self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status

Command

02H

CS#

SCLK

9 10

28 29 30 31

23 22 21

24-bit address

42 43 44 45

46 47

50 51 52 53

54 55

CS#

SCLK

MSB

Data Byte 2

32 33 34 35

MSB

Data Byte 1

Data Byte 3

Data Byte 256

MSB

36 37 38 39

GD25WD20CSFG Datasheet(PDF) 19 Page - GigaDevice Semiconductor (Beijing) Inc.

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