T25LQ128AFIPR datasheet(2/74 Pages) HMSEMI

2 / 74 page

Contents

FEATURES................................................................................................................................................................. 5

GENERAL DESCRIPTION.......................................................................................................................................5

1. ORDERING INFORMATION....................................................................................................................... 7

2. BLOCK DIAGRAM........................................................................................................................................ 8

3. CONNECTION DIAGRAMS........................................................................................................................ 9

4. SIGNAL DESCRIPTIONS..........................................................................................................................10

4.1. Serial Data Input (DI) / IO0.............................................................................................................10

4.2. Serial Data Output (DO) / IO1....................................................................................................... 10

4.3. Serial Clock (CLK)........................................................................................................................... 10

4.4. Chip Select (CS#)............................................................................................................................10

4.5. Write Protect (WP#) / IO2...............................................................................................................11

4.6. HOLD (HOLD#) / IO3...................................................................................................................... 11

4.7. RESET (RESET#) / IO3..................................................................................................................11

5. MEMORY ORGANIZATION...................................................................................................................... 12

5.1. Flash Memory Array........................................................................................................................ 12

5.2. Security Registers............................................................................................................................12

5.2.1 Security Register 0................................................................................................................13

5.2.2 Serial Flash Discoverable Parameters (SFDP) Address Map.......................................13

5.2.3 SFDP Header Field Definitions........................................................................................... 14

5.2.4 JEDEC SFDP Basic SPI Flash Parameter....................................................................... 15

6. FUNCTION DESCRIPTION...................................................................................................................... 20

6.1 SPI Operations..................................................................................................................................20

6.1.1 SPI Modes.............................................................................................................................. 20

6.1.2 Dual SPI Modes.....................................................................................................................20

6.1.3 Quad SPI Modes................................................................................................................... 20

6.1.4 QPI Function.......................................................................................................................... 21

6.1.5 Hold Function.........................................................................................................................21

6.1.6 Software Reset & Hardware RESET# pin.........................................................................21

6.2. Status Register.................................................................................................................................22

6.2.1 BUSY.......................................................................................................................................24

6.2.2 Write Enable Latch (WEL)................................................................................................... 24

6.2.3 Block Protect Bits (BP2, BP1, BP0)................................................................................... 24

6.2.4 Top / Bottom Block Protect (TB)..........................................................................................24

6.2.5 Sector / Block Protect (SEC)...............................................................................................25

6.2.6 Complement Protect (CMP)................................................................................................ 25

6.2.7 The Status Register Protect (SRP1, SRP0)..................................................................... 25

6.2.8 Erase / Program Suspend Status (SUS)...........................................................................25

6.2.9 Security Register Lock Bits (LB3, LB2, LB1)....................................................................25

6.2.10 Quad Enable (QE)...............................................................................................................26

6.2.11 HOLD# or RESET# Pin Function (HRSW)..................................................................... 26

6.2.12 Output Driver Strength (DRV1, DRV0)............................................................................26

6.2.13 High Frequency Enable Bit (HFQ)................................................................................... 26

6.2.14 Write Protect Selection (WPS)..........................................................................................26

6.2.15 Latency Control (LC)...........................................................................................................26

6.3. Write Protection................................................................................................................................27

6.3.1 Write Protect Features..........................................................................................................27

6.3.2 Block Protection Maps..........................................................................................................29

6.4. Page Program.................................................................................................................................. 32

6.5. Sector Erase, Block Erase and Chip Erase................................................................................ 32

6.6. Polling during a Write, Program or Erase Cycle.........................................................................32

6.7. Active Power, Stand-by Power and Deep Power-Down Modes.............................................. 32

7. INSTRUCTIONS..........................................................................................................................................33

7.1 Configuration and Status Commands........................................................................................... 39

7.1.1 Read Status Register (05h/35h/15h)................................................................................. 39

HM25Q128A

T25LQ128AFIPR Datasheet(PDF) 2 Page - Shenzhen Huazhimei Semiconductor Co., Ltd

T25LQ128AFIPR Datasheet(HTML) 2 Page - Shenzhen Huazhimei Semiconductor Co., Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL