ADA4945-1ACPZ-R2 datasheet(41/44 Pages) AD

41 / 44 page

Data Sheet

ADA4945-1

Rev. 0 | Page 41 of 44

OUTPUT CLAMPS

The ADA4945-1 implements output voltage clamps to effectively

limit the differential and common-mode signal levels, thereby

protecting circuitry following the ADA4945-1 from being

overdriven. The operation of these clamps is discussed in the

Theory of Operation section. Figure 113 shows an example where

the output voltage clamp may be used while driving an ADC. In

this example, the ADA4945-1 is operating from +7 V and −2 V

supplies, and the ADC is using +5 V reference. In such a scenario,

the ADC input can potentially be overdriven if no clamping were

present. By connecting the clamps to the positive and negative

references of the ADC, the differential and common-mode signal

levels are limited as shown in Figure 114 and Figure 115. Note that

the differential signals are clamped ~500 mV beyond the clamp set

voltage to allow full swing to the references. The common-mode

signal is clamped right at the clamp set voltages.

ADA4945-1

+7V

–2V

+2.5V

ADC

–IN

+IN

VREF

REF

+VCLAMP

+5V

–VCLAMP

Figure 113. ADA4945-1 Output Voltage Clamp Usage

TIME (µs)

+VS = +7V, –VS = –2V

+VCLAMP = +5V, –VCLAMP = 0V

VOCM = +2.5V

+DIN

–DIN

+OUT

–OUT

Figure 114. Clamped Differential Signal Levels

TIME (µs)

+VS = +7V, –VS = –2V

+VCLAMP = +5V, –VCLAMP = 0V

+DIN = –DIN = 0V

VOCM

+OUT, –OUT

Figure 115. Clamped Common-Mode Signal Levels

ADA4945-1ACPZ-R2 Datasheet(PDF) 41 Page - Analog Devices

ADA4945-1ACPZ-R2 Datasheet(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL