BSP3505D datasheet(2/40 Pages) MICRONAS

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BSP 3505D

PRELIMINARY DATA SHEET

Micronas

Contents

Page

Section

Title

Introduction

1.1.

BSP 3505D Integrated Functions

1.2.

Features of the DSP-Section

1.3.

Features of the Analog Section

Architecture of the BSP 3505D

2.1.

Analog Section and SCART Switching Facilities

2.1.1.

Standby Mode

2.2.

BSP 3505DAudio Baseband Processing

2.3.

Clock and Crystal Specifications

2.4.

Digital Control Output Pins

73.

I2C Bus Interface: Device and Subaddresses

3.1.

Protocol Description

3.2.

Proposal for BSP 3505D I2C Telegrams

3.2.1.

Symbols

3.2.2.

Write Telegrams

3.2.3.

Read Telegrams

3.2.4.

Examples

3.3.

Start Up Sequence: Power Up and I2C-Controlling

Programming the BSP 3505D

4.1.

4.2.

DSP Write Registers: Table and Addresses

4.3.

DSP Read Registers: Table and Addresses

4.4.

DSP Write Registers: Functions and Values

4.4.1.

Volume Loudspeaker Channel

4.4.2.

Balance Loudspeaker Channel

4.4.3.

Bass Loudspeaker Channel

4.4.4.

Treble Loudspeaker Channel

4.4.5.

Loudness Loudspeaker Channel

4.4.6.

Spatial Effects Loudspeaker Channel

4.4.7.

Volume SCART1

4.4.8.

Channel Source Modes

4.4.9.

Channel Matrix Modes

4.4.10.

SCART Prescale

4.4.11.

Definition of Digital Control Output Pins

4.4.12.

Definition of SCART-Switching Facilities

4.4.13.

Beeper

4.4.14.

Automatic Volume Correction (AVC)

4.5.

DSP Read Registers: Functions and Values

4.5.1.

Quasi-Peak Detector

4.5.2.

BSP Hardware Version Code

4.5.3.

BSP Major Revision Code

4.5.4.

BSP Product Code

4.5.5.

BSP ROM Version Code

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