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ADPA7002CHIP Datasheet(PDF) 16 Page - Analog Devices |
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ADPA7002CHIP Datasheet(HTML) 16 Page - Analog Devices |
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16 / 23 page  ADPA7002CHIP Data Sheet Rev. 0 | Page 16 of 23 ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS Figure 53. Assembly Diagram Figure 54. Typical Application Circuit Figure 55. Simplified Internal ADPA7002CHIP Block Diagram Figure 56. Power Detector Circuit DIE SIZE 2750µm × 1805µm BAR CAPACITOR 100pF 0.01µF 0.01µF RFOUT RFIN VDD1 VGG1 RFOUT ADPA7002CHIP RFIN VDD2A VDD2B 4.7µF 0.01µF 100pF + VGG1 4.7µF + VDD1 100pF 100pF VDD1 100pF 1 12 13 17 18 20 VDD3A VDD4A VGG1 VGG2 VDD3B VDD4B VDD1 VDD2 RFOUT RFIN NOTES 1. VDD3A IS A DRAIN BIAS PAD FOR THE FIRST STAGE. VDD3B IS A DRAIN BIAS PAD FOR THE SECOND STAGE. VDD4A AND VDD4B ARE A COMBINED DRAIN BIAS PAD FOR THE THIRD STAGE. COUPLED LINE RFIN VREF RFOUT VDET |
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