ADRF5046

Data Sheet

Rev. 0 | Page 10 of 15

THEORY OF OPERATION

The ADRF5046 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V,

and no dc blocking is required at the RF ports when the RF line

potential is equal to 0 V. The RF ports are internally matched to

50 Ω. Therefore, external matching networks are not required.

The ADRF5046 integrates a driver to perform logic functions

internally and to provide the user with the advantage of a simplified

CMOS/LVTTL-compatible control interface. The driver features

two digital control input pins (V1 and V2) that control the state

of the RFx paths. The logic level applied to the V1 and V2 pins

determines which RFx port is in the insertion loss state while

the other three paths are in the isolation state (see Table 5).

The insertion loss path conducts the RF signal between the

selected RF throw port and the RF common port. The switch

design is bidirectional with equal power handling capabilities.

The RF input signal can be applied to the RFC port or the

selected RF throw port. The isolation paths provide high loss

between the insertion loss path and the unselected RF throw

ports that are reflective.

The ideal power-up sequence is as follows:

1.

Connect GND.

2.

Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3.

Apply digital control inputs V1 and V2. Applying these

digital control inputs before applying the VDD supply

inadvertently forwards bias and damages the internal ESD

protection structures. To avoid this damage, use a series 1

kΩ resistor to limit the current flowing into the control

pin. Use pull-up or pull-down resistors if the controller

output is in a high impedance state after VDD is powered

up and the control pins are not driven to a valid logic state.

4.

Apply an RF input signal to either the RFC port or the RF

throw port.

The ideal power-down sequence is the reverse order of the

power-up sequence.

Table 5. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

V1

V2

RF1 to RFC

RF2 to RFC

RF3 to RFC

RF4 to RFC

Low

Low

Insertion loss (on)

Isolation (off )

Isolation (off )

Isolation (off )

High

Low

Isolation (off )

Insertion loss (on)

Isolation (off )

Isolation (off )

Low

High

Isolation (off )

Isolation (off )

Insertion loss (on)

Isolation (off )

High

High

Isolation (off )

Isolation (off )

Isolation (off )

Insertion loss (on)