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LXT975BHC Datasheet(PDF) 25 Page - Intel Corporation

Part # LXT975BHC
Description  Fast Ethernet 10/100 Quad Transceivers
PDF  74 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

LXT975BHC Datasheet(HTML) 25 Page - Intel Corporation

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Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Datasheet
25
MII Interrupts
The LXT974/975 provides interrupt signals in two ways. The MDIO interrupt reflects the interrupt
status of each port addressed by the read. Details are shown in Figure 10.
Setting bit 17.1 = 1 on all four ports, enables global interrupts using the MDINT pin. An active
Low on this pin indicates a status change on the LXT974/975. Interrupts may be caused by:
• Link status change
• Auto-negotiation complete
• Full-duplex status change
• Jabber detect
2.2.3
Hardware Control Interface
The Hardware Control Interface is used to configure operating characteristics of the LXT974/975.
When MDDIS is Low, this interface provides initial values for the MDIO registers, and then
passes control to the MDIO Interface. When MDDIS is High, this interface provides continuous
control over the LXT974/975.
Figure 8. Management Interface - Read Frame Structure
Figure 9. Management Interface - Write Frame Structure
MDC
MDIO
(Read)
32 "1"s
011
0
Preamble
SFD
Op Code
PHY Address
Turn
Around
Z0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
Data
Idle
Write
Read
D15
D14
D1
D0
Idle
MDC
MDIO
(Write)
32 "1"s
01
01
Preamble
SFD
Op Code
PHY Address
Turn
Around
1
0
A4
A3
A0
R4
R3
R0
Register Address
D15
D14
D1
D0
Data
Idle
Idle
Write
Figure 10. MDIO Interrupt Signaling
MDC
MDIO
Interrupt
Turn
Around
Z
Idle
0
INT
Read Data
Sourced by PHY
MDIO FRAME



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