82801DB datasheet(21/587 Pages) INTEL

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Intel® 82801DB ICH4 Datasheet

5-21

Short Message.............................................................................................117

5-22

APIC Bus Status Cycle Definition ................................................................ 118

5-23

Lowest Priority Message (Without Focus Processor) .................................. 119

5-24

Remote Read Message ............................................................................... 120

5-25

Interrupt Message Address Format .............................................................123

5-26

Interrupt Message Data Format ...................................................................124

5-27

Stop Frame Explanation .............................................................................. 125

5-28

Data Frame Format...................................................................................... 126

5-29

Configuration Bits Reset By RTCRST# Assertion ....................................... 129

5-30

INIT# Going Active.......................................................................................131

5-31

NMI Sources ................................................................................................ 132

5-32

DP Signal Differences.................................................................................. 132

5-33

Frequency Strap Behavior Based on Exit State........................................... 134

5-34

Frequency Strap Bit Mapping ...................................................................... 134

5-35

General Power States for Systems Using Intel® ICH4 ................................ 135

5-36

State Transition Rules for Intel® ICH4 ......................................................... 136

5-37

System Power Plane.................................................................................... 137

5-38

Causes of SMI# and SCI ............................................................................. 138

5-39

Break Events................................................................................................ 139

5-40

Sleep Types ................................................................................................. 142

5-41

Causes of Wake Events............................................................................... 143

5-42

GPI Wake Events......................................................................................... 143

5-43

Transitions Due to Power Failure................................................................. 144

5-44

Transitions Due to Power Button ................................................................. 146

5-45

Transitions Due to RI# Signal ...................................................................... 147

5-46

Write Only Registers with Read Paths in ALT Access Mode....................... 149

5-47

PIC Reserved Bits Return Values................................................................ 150

5-48

5-49

Intel® ICH4 Clock Inputs .............................................................................. 152

5-50

Alert on LAN* Message Data ....................................................................... 158

5-51

GPIO Implementation .................................................................................. 159

5-52

IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select) ..... 163

5-53

IDE Transaction Timings (PCI Clocks) ....................................................... 164

5-54

Interrupt/Active Bit Interaction Definition...................................................... 168

5-55

UltraATA/33 Control Signal Redefinitions .................................................... 169

5-56

Frame List Pointer Bit Description ............................................................... 172

5-57

TD Link Pointer ............................................................................................ 173

5-58

TD Control and Status ................................................................................. 174

5-59

TD Token ..................................................................................................... 176

5-60

TD Buffer Pointer ......................................................................................... 176

5-61

Queue Head Block.......................................................................................177

5-62

Queue Head Link Pointer............................................................................. 177

5-63

Queue Element Link Pointer ........................................................................ 177

5-64

Command Register, Status Register, and TD Status Bit Interaction ........... 180

5-65

Queue Advance Criteria............................................................................... 182

5-66

USB Schedule List Traversal Decision Table .............................................. 183

5-67

PID Format................................................................................................... 185

5-68

PID Types ....................................................................................................185

5-69

Address Field ............................................................................................... 186

5-70

Endpoint Field .............................................................................................. 186

5-71

Token Format............................................................................................... 187

82801DB Datasheet(PDF) 21 Page - Intel Corporation

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