Gran-Jansen AS Oslo Norway
98-05
7
Table 7: Bit function and position
N1
N0
M1
M0
Bypass
LNA
p46
RxOutD RxOutD_S
Fc0
Fc1
transmit
518
518
191
191
0
0
0
0
1
0
receive
518
518
191
191
0
0
0
0
1
0
RecSel
RxOut
BiasS
p54
GmBias
Mod1
Mod0
R_T
Pd
transmit
1
010
11
0
1
0
receive
1
0
1
0
1
1
0
0
0
Binary form: (MSB to the left):
Transmit:
001000000110
001000000110
0010111111
0010111111
000010101011010
Receive:
001000000110
001000000110
0010111111
0010111111
000010101011000
The 59 bit control-word is first read into a shift-register,
and is then loaded into a parallel register by a pulse on
the Load line. The circuit then goes directly into the
specified mode (receive, transmit, etc.). The time the
circuit takes to stabilise in the new mode (for instance the
time the synthesiser uses to lock on the specified
frequency) is used to clock the next control-word into the
shift-register. In transmit mode the power amplifier is not
active until the next control-word is clocked into the shift-
register. Every bit of the control-word that is clocked into
the shift-register is counted.
When all the bits have been shifted into the register (59
bits) the counter disables further bits to be clocked in. All
clock-pulses after this time are discarded. The circuit is
now ready to receive or transmit. The circuit remains in
the specified mode until the next load pulse.
As long as the circuit has power the values in the registers
are kept. When the power is turned on (for instance
when batteries are changed) a pulse on the Load line is
necessary to reset the registers and the counter
1
2
3
Clock
Load
Data XO
Figure 6: Timing of Clock, Load and Data IXO lines
1: Control-word is loaded into the second register
2: On the first positive clock edge a new control-word starts to be clocked into the shift register
3: After 59 clock pulses the circuit is ready to receive, transmit or sleep. The Data IXO line is now
Independent of the Clock line. The Clock line should now be static to minimise noise.
Table 8: Serial I/O Timing Data
Parameter
Min.
Typ.
Max.
Unit
Set up time data to clock
50
ns
Hold time data to clock
+20
ns
Strobe pulse width
50
ns
Clock frequency
10
MHz
Clock pulse width ( high)
50
ns
Table 9: Digital I/O Electrical specifications
Parameter
Min.
Typ.
Max.
Unit
Logic Low
0.2
VDD
Logic High
0.7
VDD
3 State Leakage Current
100
nA
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
