ST72311 datasheet(82/94 Pages) STMICROELECTRONICS

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ST72311

6.5 PERIPHERAL CHARACTERISTICS

Notes:

1. The safe reset cannot be guaranted by the LVD when fosc is greater than 8MHz.

2. Based on characterisation results, not tested.

(TA = -40°C to +85°C and VDD = 5V±10% unless otherwise specified )

Note: Noise at VDDA, VSSA <10mV, VDD - 0.3 V ≤ VDDA ≤ VDD, VSS ≤ VSSA ≤ VSS + 0.3 V

Figure 43. ADC Conversion characteristics

Low Voltage Detection Reset Electrical Specifications (Option)

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

VLVDUP

LVD Reset Trigger, VDD rising edge

fOSC = 8 MHz max

1).

4.1

VLVDDOWN

LVD Reset Trigger, VDD falling edge

3.35

3.85

VLVDHYS

LVD Reset Trigger, hysteresis2)

250

Analog to Digital Converter Electrical Specifications

Symbol

Parameter

Test Conditions

Value

Unit

Min.

Typ.

Max.

Res

Resolution

Bit

DLE

ILE

Differential linearity error

Integral linearity error

fOSC = 4 to 16 MHz

±0.3

±0.5

±1

LSB

Conversion Time

fOSC = 16 MHz

µs

(2)

(1)

(3)

(4)

(5)

VR02133A

Offset Error OSE

Gain Error GE

1 LSB (ideal)

1LSB

ideal

refP

refM

–

256

----------------------------------------

Vin(A) (LSBideal)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DLE)

(4) Integral non-linearity error (ILE)

(5) Center of a step of the actual transfer curve

code

out

255

254

253

252

251

250

250 251 252 253 254 255 256

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