Low Voltage CMOS Logic – 54LVC1G34

Single Buffer Gate in bare die form

Rev 1.0

29/06/19

Features:

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

420 x 380

17 x 15

µm

mils

Minimum Bond Pad Size

76 x 76

2.99 x 2.99

µm

mils

Die Thickness

280 (±20)

11.02 (±0.79)

µm

mils

Top Metal Composition

Al-Si-Cu 3 µm

Back Metal Composition

N/A – Bare Si

Inputs directly interface TTL

The 54LVC1G34 single buffer gate performs the

Boolean function Y = A. The inverter can be driven by

either 3.3V or 5V inputs enabling use of this device in a

mixed 3.3V and 5V environment. The 54LVC1G34

operates over a 1.65V to 5.5V supply range with low

power consumption and is fully specified for partial

disables the output, preventing damaging backflow

current through the device when it is powered down.

The device suits level translation and interfacing TTL to

CMOS logic applications at low power.

Inputs accept up to 5.5V enabling level translation

Low Quiescent Current: 10µA max

Tiny die size.

Die Dimensions in µm (mils)

Ordering Information

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

420 (17)

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 280µm(11 Mils) – On request

Assembled into Ceramic Package – On request

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