Low Voltage CMOS Logic – 74LVC1G34

Single Buffer Gate in bare die form

Rev 1.0

29/06/19

Features:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Die Size (Unsawn)

420 x 380

17 x 15

µm

mils

Minimum Bond Pad Size

76 x 76

2.99 x 2.99

µm

mils

Die Thickness

280 (±20)

11.02 (±0.79)

µm

mils

Top Metal Composition

Al-Si-Cu 3 µm

Back Metal Composition

N/A – Bare Si

Inputs directly interface TTL

The 74LVC1G34 single buffer gate performs the

Boolean function Y = A. The inverter can be driven by

either 3.3V or 5V inputs enabling use of this device in a

mixed 3.3V and 5V environment. The 74LVC1G34

operates over a 1.65V to 5.5V supply range with low

power consumption and is fully specified for partial

disables the output, preventing damaging backflow

current through the device when it is powered down.

The device suits level translation and interfacing TTL to

CMOS logic applications at low power.

Inputs accept up to 5.5V enabling level translation

Low Quiescent Current: 4µA max

Tiny die size.

Ordering Information

Description

Die Dimensions in µm (mils)

420 (17)

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

For High Reliability versions of this product please see

54LVC1G34

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 280µm(11 Mils) – On request

Assembled into Ceramic Package – On request

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