Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

74LVC8T595 Datasheet(PDF) 21 Page - Nexperia B.V. All rights reserved

Part # 74LVC8T595
Description  Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state
PDF  33 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NEXPERIA [Nexperia B.V. All rights reserved]
Direct Link  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved

74LVC8T595 Datasheet(HTML) 21 Page - Nexperia B.V. All rights reserved

Back Button 74LVC8T595 Datasheet HTML 17Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 18Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 19Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 20Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 21Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 22Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 23Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 24Page - Nexperia B.V. All rights reserved 74LVC8T595 Datasheet HTML 25Page - Nexperia B.V. All rights reserved Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 33 page
background image
Nexperia
74LVC8T595
Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state
74LVC8T595
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 9 May 2017
21 / 33
10.1 Waveforms and test circuit
mna557
SHCP input
Q7S output
tPLH
tPHL
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Measurement points are given in Table 16.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 7.  The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
mna558
STCP input
Qn output
tPLH
tPHL
tW
tsu
1/fmax
VM
VOH
VI
GND
VOL
VM
SHCP input
VI
GND
VM
Measurement points are given in Table 16.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 8.  The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width
and the shift clock to storage clock set-up time



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com