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74LVC30APW Datasheet(PDF) 7 Page - Nexperia B.V. All rights reserved |
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74LVC30APW Datasheet(HTML) 7 Page - Nexperia B.V. All rights reserved |
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7 / 13 page ![]() Nexperia 74LVC30A 8-input NAND gate VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aaf615 VCC VI VO DUT CL RT RL PULSE GENERATOR Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig. 7. Test circuit for measuring switching times Table 8. Test data Input Load Supply voltage VI tr, tf CL RL 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 74LVC30A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 2 — 15 March 2019 7 / 13 |
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