7

ATF1502ASV

1615H–PLD–2/04

All power-down AC characteristic parameters are computed from external input or I/O

pins, with reduced-power bit turned on. For macrocells in reduced-power mode

The ATF1502ASV macrocell also has an option whereby the power can be reduced on

a per-macrocell basis. By enabling this power-down option, macrocells that are not used

in an application can be turned down, thereby reducing the overall power consumption

of the device.

Each output also has individual slew rate control. This may be used to reduce system

noise by slowing down outputs that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast switching in the design file.

Design Software

Support

ATF1502ASV designs are supported by several third-party tools. Automated fitters allow

logic synthesis using a variety of high-level description languages and formats.

Power-up Reset

The ATF1502ASV is designed with a power-up reset, a feature critical for state machine

tialized, and the state of each output will depend on the polarity of its buffer. However,

system, the following conditions are required:

1.

2.

After reset occurs, all input and feedback setup times must be met before

driving the clock pin high, and,

3.

and Large. To ensure a robust operating environment in applications where the device

is operated near 3.0V, Atmel recommends that during the fitting process users configure

the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel

POF2JED users should include the flag “-power_reset” on the command line after “file-

name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis

option selected, the following condition is added:

4.

on again.

amps as well.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF1502ASV fuse pat-

terns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature

remains accessible.

Programming

ATF1502ASV devices are in-system programmable (ISP) devices utilizing the 4-pin

JTAG protocol. This capability eliminates package handling normally required for pro-

gramming and facilitates rapid design iterations and field changes.

Atmel provides ISP hardware and software to allow programming of the ATF1502ASV

via the PC. ISP is performed by using either a download cable, a comparable board

tester or a simple microprocessor interface.