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ICM200E
2 Megapixel (UXGA) Digital Color CMOS Image Sensor
Preliminary Data Sheet V1.1
Copyright 2004, IC Media Corporation
9/22/2004
http://www.ic-media.com/
Page 21
Table 2. SIF Registers Descriptions
(continued)
Bit Description
Default
Affected by
Latent
Register
Frame
Boundary
Update
0xAB AD_VSYNC_ENDL_C
0xAC AD_VSYNC_ENDH_C
Reserved*
0x0003
(3)
N
Y
0xAD AD_PART_CONTROL_C
Reserved*
0x00
N
Y
0xAE AD_WT_BEGINL_C
0xAF AD_WT_BEGINH_C
Reserved*
0x0000
N
Y
0xB0 AD_WT_ENDL_C
0xB1 AD_WT_ENDH_C
Reserved*
0x07F8
(2040)
N
Y
0xB2 and 0xB3
Reserved*
0x0000
Y
Y
0xB4 AD_PLL
[7:0] The PLL setting for the ADC clock. For example, at
6 MHz input, selecting 0x03 would run the system ADC
clock at 24 MHz. Note: The maximum ADC clock is
96MHz for 30 fps operation.
The default value is 0x01, for a "2x" PLL multiplier.
Setting
PLL Multiplier
0x00
1x
0x01
2x
0x02
3x
0x03
4x
…
0x1F
32x
0x01
N
Y
0xB5
Reserved*
0x00
Y
Y
0xB6 AD_F_MAX_ADDRL
0xB7 AD_F_MAX_ADDRH
Reserved*
0x04B9
(1209)
Y
Y
0xB8 AD_F_OVERL
0xB9 AD_F_OVERH
Reserved*
0x04BA
(1210)
Y
Y
0xBA AD_F_LIMITAL
0xBB AD_F_LIMITAH
Reserved*
0x04BB
(1211)
Y
Y
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