EM6124 datasheet(2/25 Pages) EMMICRO

2 / 25 page

EM6124

www.emmicroelectronic.com

Absolute Maximum Ratings

Parameter

Symbol

Conditions

Supply voltage range

VDD1,2

-0.3V to 6V

Supply high voltage range

VHV

-0.3V to 6V

Internal generated VLCD

VLCD

Voltage at DI, DO, CLK, FR,

RES

VLOGIC

-0.3V to

VDD+0.3V

Voltage at S1 to S121

VDISP

-0.3V to

VLCD+0.3V

Storage temperature range

TSTO

-65 to +150°C

Electrostatic discharge max. to

MIL-STD-883C method 3015.7

with ref. to VSS

VSmax

1000V

Maximum soldering conditions

TSmax

250°C x 10s

Stresses above these listed maximum ratings may cause

permanent damages to the device. Exposure beyond

specified operating conditions may affect device reliability

or cause malfunction.

Handling Procedures

This device has built-in protection against high static

voltages or electric fields; however, anti-static precautions

must be taken as for any other CMOS component. Unless

otherwise specified, proper operation can only occur when

all terminal voltages are kept within the voltage range.

Unused inputs must always be tied to a defined logic

voltage level.

Operating Conditions

Parameter

Symbol Min

Typ

Max Unit

Operating

Temperature

-40

+85

°C

Logic supply voltage

VDD1,2

5.5

Supply high voltage

VHV

2.5

5.5

Electrical Characteristics

VDD1 = VDD2 = 3V, VHV = 2.5 to 5V and TA = -40 to +85°C, unless otherwise specified

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Units

Standby supply current

IDD

See note 1

µA

Standby supply current

IHV

See note 1, VLCD step 30 (hexa)

170

µA

Dynamic supply current

IDD

See note 2

µA

Standby supply current

IHV

See note 3, VLCD Step 00 (hexa)

140

µA

Sleep mode supply current

IDD

0.1

µA

Sleep mode supply current

IHV

0.1

µA

Control Signals DI, CLK,

FR, RES1, RES2

Input leakage

IIN

VDD1,2 or VSS

-1

µA

Input capacitance

CIN

at TA = 25°C

Low level input voltage

VIL

0.3 VDD1,2

High level input voltage

VIH

0.7 VDD1,2

VDD1,2

DC output component

±VDC

See table 4

100

VLCD (internally generated)

VLCD

See note 4

6.15

VLCD

See note 5

3.15-7.09

VLCDstep

62.5

Table 3

Note 1: All outputs open, DI and CLK at VSS, mux ratio = 24, checker pattern.

Note 2: All outputs open, DI at VSS, fCLK = 1 MHz, mux ratio = 24, checker pattern.

Note 3: DI and CLK at VSS, checker pattern, mux ratio = 8.

Note 4: Initialization bits 18 to 23 = 110000 and initialization bits 10, 11 = 00; laser trimming on request.

Note 5: Initialization bits 18 to 23 = 000000/111111.

DC Output Component

Output

Frame

Logic Data

Measured*

Guaranteed

Row Driver

n + 1

⏐

VLCD - V2

⏐

V4 - VSS

⏐

V1 = 0.83 x VLCD ± 100 mV

V2 = 0.66 x VLCD ± 100 mV

Column Driver

n + 1

⏐

VLCD - V2

⏐

V3 - VSS

⏐

V3 = 0.34 x VLCD ± 100 mV

V4 = 0.17 x VLCD ± 100 mV

Table 4

*Vx =

Vx (load = +1

µA) + Vx (load = -1µA)

, mux 24 or 25 programmed, VLCD = 6V, TA = 25°C

Test is performed for multiplex rate = 25. All multiplex rate ≠ 25 are guaranteed by design. If multiplex rate ≠ 25, test will be

performed on request.

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