M41T81S datasheet(10/29 Pages) STMICROELECTRONICS

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M41T81S

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WRITE Mode

In this mode the master transmitter transmits to

the M41T81S slave receiver. Bus protocol is

shown in Figure 11., page 10. Following the

START condition and slave address, a logic '0' (R/

W=0) is placed on the bus and indicates to the ad-

dressed device that word address “An” will follow

and is to be written to the on-chip address pointer.

The data word to be written to the memory is

strobed in next and the internal address pointer is

incremented to the next address location on the

reception of an acknowledge clock. The M41T81S

slave receiver will send an acknowledge clock to

the master transmitter after it has received the

slave address see Figure 8., page 8 and again af-

ter it has received the word address and each data

byte.

Data Retention Mode

With valid VCC applied, the M41T81S can be ac-

cessed as described above with READ or WRITE

Cycles. Should the supply voltage decay, the pow-

er input will be switched from the VCC pin to the

battery when VCC falls below the Battery Back-up

Switchover Voltage (VSO). At this time the clock

registers will be maintained by the attached bat-

tery supply. On power-up, when VCC returns to a

nominal value, write protection continues for tREC.

For a further, more detailed review of lifetime cal-

culations, please see Application Note AN1012.

Figure 11. WRITE Mode Sequence

AI00591

BUS ACTIVITY:

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

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