CDB4365 datasheet(21/51 Pages) CIRRUS

21 / 51 page

DS670PP1

CS4365

3.2

Mode Select

In hardware mode operation is determined by the Mode Select pins. The state of these pins are continually

scanned for any changes. These pins require connection to supply or ground as outlined in figure 8. For

M0, M1, M2 supply is VLC and for M3 and M4 supply is VLS. Tables 4 - 6 show the decode of these pins.

In software mode the operational mode and data format are set in the FM and DIF registers.

“Parameter

Definitions” on page 45.

(DIF1)

(DIF0)

DESCRIPTION

FORMAT

FIGURE

Left Justified, up to 24-bit data

I2S, up to 24-bit data

110

Right Justified, 16-bit Data

211

Right Justified, 24-bit Data

312

Table 4. PCM Digital Interface Format, Hardware Mode Options

(DEM)

DESCRIPTION

Single-Speed without De-Emphasis (4 to 50 kHz sample rates)

Single-Speed with 44.1 kHz De-Emphasis; see Figure 18

Double-Speed (50 to 100 kHz sample rates)

Quad-Speed (100 to 200 kHz sample rates)

Auto Speed-Mode Detect (32 kHz to 200 kHz sample rates)

Auto Speed-Mode Detect with 44.1 kHz De-Emphasis; see Figure 18

DSD Processor Mode (see Table 6 for details)

Table 5. Mode Selection, Hardware Mode Options

DESCRIPTION

000

64x oversampled DSD data with a 4x MCLK to DSD data rate

001

64x oversampled DSD data with a 6x MCLK to DSD data rate

010

64x oversampled DSD data with a 8x MCLK to DSD data rate

011

64x oversampled DSD data with a 12x MCLK to DSD data rate

100

128x oversampled DSD data with a 2x MCLK to DSD data rate

101

128x oversampled DSD data with a 3x MCLK to DSD data rate

110

128x oversampled DSD data with a 4x MCLK to DSD data rate

111

128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 6. Direct Stream Digital (DSD), Hardware Mode Options

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