CS6403-IL datasheet(13/54 Pages) CIRRUS

13 / 54 page

cept for the SSI, though writes to any control bit

except RST are ignored. Power down is not en-

abled.

Upon exiting Reset, control registers and RAM

are cleared, and then control constants are loaded

into Data RAM from the Program ROM.

Power-Down

Power Down is initiated by setting the Sleep bit

in SSI Control Register 0 (SLP: SSI_CR0.10).

In Power Down, the CPU and the AFP are pow-

ered down, but the SSI and the Codec are still

operational. Power Down is only accessible in

Mode 2 (16-bit).

Since the SSI and the Codec are active during

Power Down, it is possible to serially transfer

SDI

SCLK

SSYNC

SDO

AVDD

AGND0

CLKIN

CLKOUT

RESET

System

Reset

SPKROUTP

SPKROUTN

VREF

VCM

+5V Analog

Supply

0.1

µF

SYNCOUT

FSR

FST

BCLKR

BCLKT

MICIN

Microphone

Phantom Power

Supply

AGND1

DGND0

GPOUT0

GPOUT1

0.1

µF

2.2k

Ω

0.47

µF

0.022

µF

NPO

150

Ω

Microphone

8.192MHz

PVDD

PGND1

PGND0

µF

Ω

0.1

µF

DGND1

DVDD1

DVDD0

33 pF

CS6403

Digital

Ground

Analog

Ground

Speaker

Ground

UALAW

Ω

µF

External

µ-law

Codec

µF

MCLK

SFRAME

RESERVED1

SMASTER

470 pF

CLK_SEL

CONFIG

GPIN3

GPIN0

GPIN1

GPIN2

RESERVED2

RESERVED6

RESERVED0

RESERVED3

RESERVED4

RESERVED5

SCLK_RATE0

SCLK_RATE1

0.1

µF

0.1

µF0.1 µF0.1 µΦ0.1 µΦ

Figure 5. External Mu-law Codec Connection Diagram

CS6403

DS192PP6

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