82830MP datasheet(6/159 Pages) INTEL

6 / 159 page

Intel

® 830MP Chipset

Datasheet

298338-001

5.2.4.14

Special Cycles .............................................................................. 111

5.2.5

In-Order Queue Pipelining......................................................................... 113

5.2.6

Write Combining........................................................................................ 113

5.3

System Memory Interface ........................................................................................... 113

5.3.1

SDRAM Interface Overview ...................................................................... 113

5.3.2

SDRAM Organization and Configuration .................................................. 114

5.3.2.1

Configuration Mechanism for SO-DIMMs..................................... 114

5.3.2.1.1

Memory Detection and Initialization ........................... 114

5.3.2.1.2

SDRAM Register Programming ................................. 115

5.3.3

SDRAM Address Translation and Decoding ............................................. 115

5.3.4

SDRAM Performance Description............................................................. 116

5.4

AGP Interface .............................................................................................................. 116

5.4.1

AGP Target Operations............................................................................. 117

5.4.2

AGP Transaction Ordering ........................................................................ 118

5.4.3

AGP Electricals ......................................................................................... 118

5.4.4

Support for PCI-66 Devices....................................................................... 118

5.4.5

4x AGP Protocol........................................................................................ 118

5.4.6

Fast Writes ................................................................................................ 118

5.4.7

AGP-to-Memory Read Coherency Mechanism......................................... 119

5.4.8

PCI Semantic Transactions on AGP ......................................................... 119

5.4.8.1

PCI Read Snoop-Ahead and Buffering ........................................ 119

5.4.8.2

GMCH-M Initiator and Target Operations .................................... 120

5.4.8.3

GMCH-M Retry/Disconnect Conditions ........................................ 122

5.4.8.4

Delayed Transaction..................................................................... 122

5.5

GMCH-M Power and Thermal Management............................................................... 123

5.5.1

ACPI 2.0 Support ...................................................................................... 123

5.5.2

ACPI States Supported ............................................................................. 123

5.5.3

Intel 830MP Chipset System and CPU States .......................................... 125

5.5.4

Intel 830MP Chipset CPU “C” States ........................................................ 125

5.5.4.1

Full-On (C0) .................................................................................. 125

5.5.4.2

Auto-Halt (C1)............................................................................... 125

5.5.4.3

Quickstart (C2).............................................................................. 125

5.5.4.4

Deep Sleep (C3) ........................................................................... 126

5.5.5

Intel 830MP Chipset AGP_BUSY# Protocol with External Graphics........ 126

5.5.6

Intel SpeedStep

 Technology .................................................................. 126

5.5.7

Intel 830MP Chipset System “S” States.................................................... 127

5.5.7.1

Powered-On-Suspend (POS) (S1) .............................................. 127

5.5.7.2

Suspend-To-RAM (STR) (S3) ...................................................... 127

5.5.7.3

S4 (SUSPEND TO DISK), S5 (Soft Off) State ............................. 127

5.5.8

System Memory Dynamic CKE support.................................................... 127

5.5.9

GMCH-M Thermal Management............................................................... 128

5.5.9.1

System Bandwidth Monitoring and Throttling............................... 128

5.6

Clocking....................................................................................................................... 128

5.7

XOR Test Chains......................................................................................................... 128

5.7.1.1

Test Mode Entry ........................................................................... 128

5.7.1.2

RAC Chain Initialization................................................................ 129

5.7.1.3

XOR Chain Test Pattern Consideration for Differential Pairs....... 131

5.7.1.4

XOR Chain Exclusion List ............................................................ 132

5.7.1.5

NC Balls........................................................................................ 133

5.7.1.6

XOR Chain Connectivity/Ordering................................................ 134

Performance............................................................................................................................. 146

Mechanical Specification.......................................................................................................... 147

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