TSB41AB3IPFPEP datasheet(46/52 Pages) TI

46 / 52 page

TSB41AB3EP

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS122B − JULY 2002 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interface reset and disable (continued)

The sequence of events for disabling the PHY-LLC interface when it is in the nondifferentiated mode of operation

(ISO terminal is high) is as follows:1

Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet

data reception and transmission via the CTL and D lines, and request activity via the LREQ line.

LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any

interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset

state.

Interface disabled. If the LPS signal remain inactive for TLPS_DISABLE time, the PHY terminates

SYSCLK activity by driving the SYSCLK output low. The PHY-LLC interface is now in the disabled state.

After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal

operation when LPS is reasserted by the LLC. The timing for interface initialization is shown in Figure 26 and

Figure 27.

SYSCLK

ISO

(low)

(a)

(c)

(b)

CTL0

D0 − D7

LREQ

LPS

(d)

TCLK_ACTIVATE

CTL1

7 Cycles

5 ns. min

10 ns. max

Figure 26. Interface Initialization, ISO Low

TSB41AB3IPFPEP Datasheet(PDF) 46 Page - Texas Instruments