9

Logic Inputs

The A/B select, logic input, is internally referenced to

ground. It is set at 2 diode drops above ground, to give a

threshold of about 1.4V (see Figure 27). The PNP input

transistor requires that the driving gate be able to sink

current, typically < 30µA, for a logic “low”. If left to float, it will

be a logic “high”.

The input PNP transistors have sufficient gain that a simple

level shift circuit (see Figure 28) can be used to provide a

simple interface with Emitter Coupled Logic. Typically,

200mV is enough to switch from a solid logic “low” to a

“high.”

pin’s capacitance from slowing the control signal. The

network shown level shifts the ECL levels, -0.7V to -1.5V to

is required since the open emitter of the ECL gate can not

sink current. If a -2V rail is not being used, a 220

Ω to 330Ω

resistor to the -5.2V rail would have the same effect.

FIGURE 27. SIMPLIFIED LOGIC INPUT STAGE

FIGURE 28. ADAPTING THE SELECT PIN

FOR ECL LOGIC LEVELS

EL4332