22
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP™
Omni
ision
15
COMK
00
RW
Common Control K
Bit[7]:
CHSYNC pin output swap
0:
CHSYNC
1:
HREF
Bit[6]:
HREF pin output swap
0:
HREF
1:
CHSYNC
Bit[5]:
PCLK output selection
0:
PCLK always output
1:
PCLK output qualified by HREF
Bit[4]:
PCLK edge selection
0:
Data valid on PCLK falling edge
1:
Data valid on PCLK rising edge
Bit[3]:
HREF output polarity
0:
Output positive HREF
1:
Output negative HREF, HREF negative for data valid
Bit[2]:
Reserved
Bit[1]:
VSYNC polarity
0:
Positive
1:
Negative
Bit[0]:
HSYNC polarity
0:
Positive
1:
Negative
16
RSVD
XX
–
Reserved
17
HREFST
1D
(13 in
VGA)
RW
Horizontal Window Start Most Significant 8 bits, LSB in register
COMM[1:0] (see “COMM” on page 26).
HREFST[9:0]: Selects the beginning of the horizontal window,
each LSB represents two pixels. Adjustment steps
must be 2 pixels.
Note:
1. HFREFST[9:0] should be less than HREFEND[9:0].
2. For maximum output window size of 1292x1024, minimum value of
this register is 0x1C.
18
HREFEND
BD
(63 in
VGA)
RW
Horizontal Window end most significant 8 bits, LSB in register
COMM[3:2] (see “COMM” on page 26).
HREFEND[9:0]: Selects the end of the horizontal window, each
LSB represents two pixels. Adjustment steps
must be 2 pixels.
Note:
1. HREFEND[9:0] should be larger than HREFST[9:0].
2. For maximum output window size of 1292x1024, maximum value of
this register is 0xBD.
Table 11
Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
Description
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