7-849

CD4034BMS

FIGURE 15. SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS

“A” PARALLEL DATA

SHIFT LEFT OUTPUT

“A” ENABLE

AE

SI

P/S

A/S

CL

A/B

1

1

8

“A” PARALLEL DATA

AE

SI

P/S

A/S

CL

A/B

1

1

8

SHIFT LEFT/

SHIFT RIGHT

SHIFT RIGHT

INPUT

CLOCK

A/S

PARALLEL

ENTRY

REG. 1

CD4034

AE

SI

P/S

A/S

CL

A/B

1

1

8

A PARALLEL DATA

8

B PARALLEL DATA

REG. 4

CD4034

REG. 2

CD4034

SHIFT RIGHT

OUTPUT

P/S

AE

SHIFT

LEFT INPUT

*

A/S

CL

AE

VDD

AE

SI

P/S

A/S

CL

A/B

1

1

8

A PARALLEL DATA

8

B PARALLEL DATA

REG. 3

CD4034

VDD

A “High” (“Low”) on the shift Left/Shift Right input allows

serial data on the Shift Left Input (Shift Right Input) to enter

the register on the positive transition of the clock signal. A

“high” on the “A” Enable Input disables the “A” parallel data

lines Reg. 1 and 2 and enables the “A” data lines on regis-

ters 3 and 4 and allows parallel data into registers 1 and 2.

FIGURE 16. N-STAGE SHIFT REGISTER WITH FIXED SERIAL

OUTPUT LINE

A PARALLEL DATA

B PARALLEL DATA

SERIAL

DATA

VDD

CLOCK

CD4034

CD4016

CD4016

N STAGE SELECTION

N = 1 - 8

SERIAL

OUTPUT

AE

SI

A/B

A/S

CL

P/S

Other logic schemes may be used in place of registers 3 and

4 for parallel loading.

When parallel inputs are not used Reg. 3 and 4 and associ-

ated logic are not required.

* Shift left input must be disabled during parallel entry.

FIGURE 17. SAMPLE AND HOLD REGISTER - SERIAL/PARAL-

LEL IN - PARALLEL OUT

AE

SI

A/B

A/S

CL

P/S

“A” PARALLEL DATA

SERIAL DATA

VDD

CLOCK

CD4034

18

“B” PARALLEL DATA

18

A/S

P/S

TO DISPLAY ETC

SAMPLE/HOLD