7-1060

CD4086BMS

FIGURE 1. SCHEMATIC DIAGRAM

FIGURE 2. TWO CD4086BMS’S CONNECTED AS AN 8-WIDE 2-INPUT A-O-I GATE

A

B

C

D

E

F

G

H

ENABLE/EXP

INHIBIT/EXP

1

2

12

13

5

6

8

9

11

10

*

*

*

*

*

*

*

*

*

*

p

n

p

p

p

n

p

n

n

p

n

p

p

n

n

n

pp

p

p

p

n

n

n

n

n

VDD

VDD

VSS

VSS

p

p

pp

n

n

nn

3

J

TERM 14 = VDD

TERM 7 = VSS

VDD

VSS

CMOS PROTECTION NETWORK

J2 = A1 B1 + C1 D1 + E1 FE + G1 H1 + A2 B2 + C2 D2 + E2 F2 + G2 H2

VSS

VDD

A1

B1

C1

D1

E1

F1

G1

H1

ENABLE/EXP1

INHIBIT/EXP1

VSS

A2

B2

C2

D2

E2

F2

G2

H2

ENABLE/EXP2

INHIBIT/EXP2

J1

J2

into the ENABLE/EXP input to obtain a 5-wide A-O-I func-

tion. In addition, and AND gate output can be fed directly into

the INHIBIT/EXP input with the same result.

Figure 2 above shows two CD4086’s utilized to obtain 8-wide

2-input A-O-I function. The output (J1) of one CD4086 is fed

directly to the ENABLE/EXP2 line of the second CD4086. In

a similar fashion, any NAND gate output can be fed directly