C

R

Output

Input Clock

Reference Clock

9

SN74HCS86

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SCLS783A – JANUARY 2020 – REVISED MAY 2020

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

In this application, a 2-input XOR gate is used as a phase difference detector as shown in Figure 9. The

remaining three gates can be used for other applications in the system, or the inputs can be grounded and the

channels left unused.

The SN74HCS86 is used to identify phase difference between a reference clock and another input clock.

Whenever the clock states are different, the XOR output will pulse HIGH until the clocks return to the same state.

The output is fed into a low-pass filter to obtain a DC representation of the phase difference.

Typically, clock signals have fast transition rates, but additional filtering can be added to the clock signals which

can lead to slower transitions rates. This makes the SN74HCS86 ideal for the application because it has Schmitt-

trigger inputs that do not have input transition rate requirements.

9.2 Typical Application

Figure 9. Typical application block diagram

9.2.1 Design Requirements

•

All signals in the system operate at 5 V

•

The XOR outputs High if any of these conditions apply:

–

Input clock is in a High state while the reference clock is in a LOW state

–

Input clock is in a LOW state while the reference clock is in a HIGH state

9.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The

supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.

The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the

only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to

The SN74HCS86 can drive a load with a total capacitance less than or equal to 50 pF connected to a high-

impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be

applied, however it is not recommended to exceed 70 pF.

Total power consumption can be calculated using the information provided in CMOS Power Consumption and

Cpd Calculation.

Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear

and Logic (SLL) Packages and Devices.