TMS320VC5416 datasheet(22/98 Pages) TI1

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TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

www.ti.com

IPTR

R/W-1FF

IPTR

MP/MC

OVLY

AVIS

DROM

CLKOFF

SMUL

SST

MP/MC pin

R/W-0

LEGEND: R = Read, W = Write, n = value present after reset

Figure 3-4. Process Mode Status Register

Table 3-2. Processor Mode Status (PMST) Register Bit Fields

BIT

RESET

FUNCTION

VALUE

NO.

NAME

Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt

vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset,

15-7

IPTR

1FFh

these bits are all set to 1; the reset vector always resides at address FF80h in program memory space.

The RESET instruction does not affect this field.

Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in

program memory space.

•

MP/MC = 0: The on-chip ROM is enabled and addressable.

MP/MC • MP/MC = 1: The on-chip ROM is not available.

MP/MC

MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset.

This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This

bit can also be set or cleared by software.

RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.

The values for the OVLY bit are:

OVLY

•

OVLY = 0: The on-chip RAM is addressable in data space but not in program space.

•

OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0

(addresses 0h to 7Fh), however, is not mapped into program space.

Address visibility mode. AVIS enables/disables the internal program address to be visible at the

address pins.

•

AVIS = 0: The external address lines do not change with the internal program address. Control

AVIS

and data lines are not affected and the address bus is driven with the last address on the bus.

•

AVIS = 1: This mode allows the internal program address to appear at the pins of the device so

that the internal program address can be traced. Also, it allows the interrupt vector to be decoded

in conjunction with IACK when the interrupt vectors reside on on-chip memory.

DROM enables on-chip DARAM4-7 to be mapped into data space. The DROM bit values are:

DROM

•

DROM = 0: The on-chip DARAM4-7 is not mapped into data space.

•

DROM = 1: The on-chip DARAM4-7 is mapped into data space.

CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high

CLKOFF

level.

Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before

SMUL

N/A

performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1

and FRCT = 1.

Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before

SST

N/A

storing in memory. The saturation is performed after the shift operation.

Functional Overview

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