LPC55S6X datasheet(42/128 Pages) NXP

42 / 128 page

LPC55S6x

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Product data sheet

Rev. 1.9 — 10 February 2020

42 of 128

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.7.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

7.8 System Tick timer (SysTick)

The ARM Cortex-M33 core include a system tick timer (SysTick) that is intended to

generate a dedicated SYSTICK exception. The clock source for the SysTick can be the

system clock or the SYSTICK clock.

7.9 On-chip static RAM

The LPC55S6x support up to 320 KB SRAM with separate bus master access for higher

throughput and individual power control for low-power operation.

7.10 On-chip flash

The LPC55S6x supports up to 640 kB of on-chip flash memory. The last 17 pages (10 KB)

are reserved on the 640 KB flash devices resulting in 630 KB internal flash memory.

7.11 On-chip ROM

The on-chip ROM contains the bootloader and the following features:

• Booting of images from on-chip flash.

• Supports CRC32 image integrity checking.

• Supports flash programming through In System Programming (ISP) commands over

following interfaces: USB0/1 interfaces using HID Class device, UART interface

(Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9) using mode 3

(CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)

• ROM API functions: Flash programming API, Power control API, and Secure firmware

update API using NXP Secure Boot file format, version 2.0 (SB2 files).

• Supports booting of images from PRINCE encrypted flash region.

• Supports NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1

(RSA-4096)

• Supports setting a sealed part to Fault Analysis mode through Debug authentication.

The on-chip ROM supports the following secure boot features:

• Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic signature

verification

• Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent)

• Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent)

• Uses x509 certificate format to validate image public keys

• Supports up to four revocable Root of Trust (or Certificate Authority) keys, Root of

Trust (RoT) establishment by storing the SHA-256 hash digest of the hashes of four

RoT public keys in protected flash region (PFR)

• Supports anti-rollback feature using image key revocation and supports up to 16

Image key certificates revocations using Serial Number field in x509 certificate.

LPC55S6X Datasheet(PDF) 42 Page - NXP Semiconductors

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