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P89LPC938FDH Datasheet(PDF) 49 Page - NXP Semiconductors |
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P89LPC938FDH Datasheet(HTML) 49 Page - NXP Semiconductors |
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49 / 68 page ![]() 9397 750 14051 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 25 February 2005 49 of 68 Philips Semiconductors P89LPC938 8-bit microcontroller with 10-bit A/D converter criteria, the boundary limits will again be compared after all 8 MSBs have been converted. A boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt. 8.7 Clock divider The A/D converter requires that its internal clock source be in the range of 500 kHz to 3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose. 8.8 Power-down and Idle mode In Idle mode the A/D converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D. |
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