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KSZ8873MML Datasheet(PDF) 21 Page - Microchip Technology |
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KSZ8873MML Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 91 page  2018 Microchip Technology Inc. DS00002776A-page 21 KSZ8873MML 3.3.7.8 Port Individual MAC Address and Source Port Filtering The KSZ8873MML provide individual MAC address for port 1 and port 2 respectively. They can be set at register 142- 147 and 148-153. The packet will be filtered if its source address matches the MAC address of port 1 or port 2 when the register 21 and 37 bit 6 is set to 1 respectively. For example, the packet will be dropped after it completes the loop of a ring network. Note that for KSZ8873MML, port 1 means port 1’s MII and an external PHY here. 3.3.8 MII INTERFACE OPERATION The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common interface between physical layer and MAC layer devices. The MII provided by the KSZ8873MML is connected to device’s first MAC as port 1 MII and third MAC as port 3 MII. The interface contains two distinct groups of signals: one for transmission and the other for reception. Table 3-3 describes the signals used by the MII bus. The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors. For half duplex operation, the SCOL signal indicates if a collision has occurred during transmission. The selection of the PHY mode and MAC mode for port3 MII is by the strap pin SMRXDV3 and the port register 53 bit 7. The selection of the PHY mode and MAC mode for port1 MII is by the strap pin SMRXD13 and the port register 21bit 7. The KSZ8873MML does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a transmit error from the MAC device. Since the switch filters error frames, these MII error signals are not used by the KSZ8873MML. So, for PHY mode operation, if the device interfacing with the KSZ8873MML has an MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8873MML has an MTXER input pin, it also needs to be tied low. The KSZ8873MML provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link status. If the host is power down, pin MII_LINK will go to high. In this case, no new ingress frames from port1 or port 2 will be sent out through port 3, and the frames for port 3 already in packet memory will be flushed out. TABLE 3-3: MII SIGNALS PHY Mode Connections Pin Description MAC Mode Connections External MAC Controller Signals KSZ8873MML Port 1,3 PHY Signals External PHY Signals KSZ8873MML Port 1,3 MAC Signals MTXEN SMTXEN Transmit Enable MTXEN SMRXDV MTXER SMTXER Transmit Error MTXER (NOT USED) MTXD3 SMTXD3 Transmit Data Bit 3 MTXD3 SMRXD3 MTXD2 SMTXD2 Transmit Data Bit 2 MTXD2 SMRXD2 MTXD1 SMTXD1 Transmit Data Bit 1 MTXD1 SMRXD1 MTXD0 SMTXD0 Transmit Data Bit 0 MTXD0 SMRXD0 MTXC SMTXC Transmit Clock MTXC SMRXC MCOL SCOL Collision Detection MCOL SCOL MCRS SCRS Carrier Sense MCRS SCRS MRXDV SMRXDV Receive Data Valid MRXDV SMTXEN MRXER (NOT USED) Receive Error MRXER SMTXER MRXD3 SMRXD3 Receive Data Bit 3 MRXD3 SMTXD3 MRXD2 SMRXD2 Receive Data Bit 2 MRXD2 SMTXD2 MRXD1 SMRXD1 Receive Data Bit 1 MRXD1 SMTXD1 MRXD0 SMRXD0 Receive Data Bit 0 MRXD0 SMTXD0 MRXC SMRXC Receive Clock MRXC SMTXC |
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