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RT1050 Datasheet(PDF) 39 Page - NXP Semiconductors |
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RT1050 Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 110 page  Electrical characteristics i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 1.4, 01/2020 NXP Semiconductors 39 Figure 11. Test access port timing diagram Figure 12. JTAG_TRST_B timing diagram Table 30. JTAG timing ID Parameter1,2 All Frequencies Unit Min Max SJ0 JTAG_TCK frequency of operation 1/(3•TDC)1 0.001 22 MHz SJ1 JTAG_TCK cycle time in crystal mode 45 — ns SJ2 JTAG_TCK clock pulse width measured at VM2 22.5 — ns SJ3 JTAG_TCK rise and fall times — 3 ns SJ4 Boundary scan input data set-up time 5 — ns SJ5 Boundary scan input data hold time 24 — ns SJ6 JTAG_TCK low to output data valid — 40 ns SJ7 JTAG_TCK low to output high impedance — 40 ns SJ8 JTAG_TMS, JTAG_TDI data set-up time 5 — ns JTAG_TCK (Input) JTAG_TDI (Input) JTAG_TDO (Output) JTAG_TDO (Output) JTAG_TDO (Output) VIH VIL Input Data Valid Output Data Valid Output Data Valid JTAG_TMS SJ8 SJ9 SJ10 SJ11 SJ10 JTAG_TCK (Input) JTAG_TRST_B (Input) SJ13 SJ12 |
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