W7500 datasheet(34/38 Pages) WIZNET

Part #	W7500

Description	Microcontrollers

PDF	38 Pages

Scroll/Zoom	100%

Manufacturer	WIZNET [WIZnet Co., Ltd]

Direct Link	https://www.wiznet.io/ko/Product/

Logo

34 / 38 page

34 / 38

5.9 Reset & PLL Characteristics

PLL Electrical characteristics

Table 20 shows the PLL characteristics of W7500x

Table 20 PLL electrical characteristics

Symbol

Parameter

Min

Max

Unit

RSTn to PD delay time

trst

Reset pulse width

tlock

Lock time

0.2

Notice:

PLL_PDR[0] is LSB of PLL_PDR. please refer from Reference Manual.

lock signal is internal signal.

1, td is the RSTn to PLL_PDR[0] delay time, which need larger than 5us.

2, trst is the reset pulse width, which need larger than 2us.

3, tlock is the lock time, which is less than 0.2ms.

4, When PLL_PDR[0] changes from “1” to “0”, the lock signal stays in “1” until a reset

pulse comes. But the PLL is in unlocked state during this period.

Figure 9 Power Down operation Timing Sequence for PLL

W7500 Datasheet(PDF) 34 Page - WIZnet Co., Ltd