®

AS7C4096A

5/27/05, v. 1.1

Alliance Semiconductor

P. 6 of 10

AC test conditions

Notes

2

For test conditions, see AC Test Conditions.

4

This parameter is guaranteed, but not tested.

5WE is HIGH for read cycle.

6CE and OE are LOW for read cycle.

7

Address valid prior to or coincident with CE transition Low.

8

All read cycle timings are referenced from the last valid address to the first transitioning address.

9

All write cycle timings are referenced from the last valid address to the first transitioning address.

10 C = 30pF, except at high Z and low Z parameters, where C = 5pF.

Address

CE

WE

Data valid

255

Ω

480

Ω

GND

+5.0V

Figure B: 5.0V Output load

- Output load: see Figure B.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

168

Ω

Thevenin equivalent:

+1.728V

10%

90%

10%

90%

GND

Figure A: Input pulse

2 ns