MSP430F5632IPZ datasheet(49/127 Pages) TI

49 / 127 page

8.45 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

VeREF+

Reference input voltage

range

DAC12IR = 0(1) (2)

2.2 V, 3 V

AVCC / 3 AVCC + 0.2

DAC12IR = 1(3) (4)

AVCC AVCC + 0.2

Ri(VREF+),

Ri(VeREF+)

Reference input resistance

DAC12_0 IR = DAC12_1 IR = 0

2.2 V, 3 V

MΩ

DAC12_0 IR = 1, DAC12_1 IR = 0

kΩ

DAC12_0 IR = 0, DAC12_1 IR = 1

DAC12_0 IR = DAC12_1 IR = 1,

DAC12_0 SREFx = DAC12_1 SREFx(5)

(1)

For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).

(2)

The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC – VE(O)) / (3 × (1 + EG)).

(3)

For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).

(4)

The maximum voltage applied at reference input voltage terminal VeREF+ = (AVCC – VE(O)) / (1 + EG).

(5)

When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel

reducing the reference input resistance.

8.46 12-Bit DAC, Dynamic Specifications

VREF = VCC, DAC12IR = 1 (see Figure 8-19 and Figure 8-20), over recommended ranges of supply voltage and

operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX UNIT

tON

DAC12 on time

DAC12_xDAT = 800h,

ErrorV(O) < ±0.5 LSB(1)

(see Figure 8-19)

DAC12AMPx = 0 → {2, 3, 4}

2.2 V, 3 V

120

µs

DAC12AMPx = 0 → {5, 6}

DAC12AMPx = 0 → 7

tS(FS)

Settling time, full scale

DAC12_xDAT =

80h → F7Fh → 80h

DAC12AMPx = 2

2.2 V, 3 V

100

200

µs

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

tS(C-C)

Settling time, code to

code

DAC12_xDAT =

3F8h → 408h → 3F8h,

BF8h → C08h → BF8h

DAC12AMPx = 2

2.2 V, 3 V

µs

DAC12AMPx = 3, 5

DAC12AMPx = 4, 6, 7

Slew rate

DAC12_xDAT =

80h → F7Fh → 80h(2)

DAC12AMPx = 2

2.2 V, 3 V

0.05

0.35

V/µs

DAC12AMPx = 3, 5

0.35

1.10

DAC12AMPx = 4, 6, 7

1.50

5.20

Glitch energy

DAC12_xDAT =

800h → 7FFh → 800h

DAC12AMPx = 7

2.2 V, 3 V

nV-s

(1)

RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 8-19.

(2)

Slew rate applies to output voltage steps ≥ 200 mV.

= 3 k

Load

= 100 pF

Load

DAC Output

O/P(DAC12.x)

Load

Conversion 1

Conversion 2

OUT

Conversion 3

Glitch

Energy

±1/2 LSB

settleLH

settleHL

Figure 8-19. Settling Time and Glitch Energy Testing

www.ti.com

MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635

MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630

SLAS650G – MAY 2010 – REVISED SEPTEMBER 2020

Submit Document Feedback

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634

MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5632IPZ Datasheet(PDF) 49 Page - Texas Instruments

MSP430F5632IPZ Datasheet(HTML) 49 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL