SiI 141B
SiI-DS-0037-C
Silicon Image, Inc.
4
Subject to Change without Notice
AC Specifications
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TDPS
Intra-Pair (+ to -) Differential Input Skew
86 MHz
470
ps
TCCS
Channel to Channel Differential Input Skew
86 MHz
7
ns
TIJIT
65 MHz
465
ps
Worst Case Differential Input Clock Jitter tolerance
1,2
86 MHz
350
ps
CL = 10pF; ST = 1
3.5
ns
Low-to-High Transition Time: Data and Controls
(43 MHz, 2-pixel/clock, PIXS=1)
CL = 5pF; ST = 0
4.5
ns
CL = 10pF; ST = 1
3.5
ns
Low-to-High Transition Time: Data and Controls
(65 MHz, 1-pixel/clock, PIXS=0)
CL = 5pF; ST = 0
4.5
ns
CL = 10pF; ST = 1
1.6
ns
Low-to-High Transition Time: ODCK
(43 MHz, 2-pixel/clock, PIXS=1)
CL = 5pF; ST = 0
2.1
ns
CL = 10pF; ST = 1
1.6
ns
DLHT
Low-to-High Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
CL = 5pF; ST = 0
2.1
ns
DHLT
CL = 10pF; ST = 1
3.0
ns
High-to-Low Transition Time: Data and Controls
(43 MHz, 2-pixel/clock, PIXS=1)
CL = 5pF; ST = 0
4.2
ns
CL = 10pF; ST = 1
3.0
ns
High-to-Low Transition Time: Data and Controls
(65 MHz, 1-pixel/clock, PIXS=0)
CL = 5pF; ST = 0
4.2
ns
CL = 10pF; ST = 1
1.5
ns
High-to-Low Transition Time: ODCK
(43 MHz, 1-pixel/clock, PIXS=0)
CL = 5pF; ST = 0
1.9
ns
CL = 10pF; ST = 1
1.5
ns
High-to-Low Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
CL = 5pF; ST = 0
1.9
ns
TSETUP
CL = 10pF; ST = 1
3.6
3.0*
ns
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to
ODCK falling edge (OCK_INV = 0) or to ODCK rising
edge (OCK_INV = 1)
*OCK_INV = 1
CL = 5pF; ST = 0
18.4
19.0*
ns
THOLD
CL = 10pF; ST = 1
8.0
8.4*
ns
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from
ODCK falling edge, (OCK_INV = 0) or from ODCK rising
edge (OCK_INV = 1)
*OCK_INV = 0
CL = 5pF; ST = 0
24.0
24.5*
ns
RCIP
ODCK Cycle Time (1 pixel/clock)
11.6
40
ns
FCIP
ODCK Frequency (1 pixel/clock)
25
86
MHz
RCIP
ODCK Cycle Time (2 pixels/clock)
23.3
80
ns
FCIP
ODCK Frequency (2 pixels/clock)
12.5
43
MHz
RCIH
ODCK High Time
65 MHz, One Pixel / Clock, PIXS = 0
3
CL = 10pF, ST=1
CL = 5pF, ST=0
5.0
4.4
ns
43 MHz, Two Pixel / Clock, PIXS = 1
3
CL = 10pF, ST=1
CL = 5pF, ST=0
9.0
8.2
ns
RCIL
ODCK Low Time
65 MHz, One Pixel / Clock, PIXS = 0
3
CL = 10pF, ST=1
CL = 5pF, ST=0
6
5
ns
43 MHz, Two Pixel / Clock, PIXS = 1
3
CL = 10pF, ST=1
CL = 5pF, ST=0
9
9
ns
THSC
Link disabled (DE inactive) to SCDT low
1
160
ms
Link disabled (Tx power down) to SCDT low
5
200
250
ms
TFSC
Link enabled (DE active) to SCDT high
6
40
Falling
DE edges
TCLKPD
Delay from RXC+/- Inactive to high impedance outputs
RXC+/- = 25MHz
10
µs
TCLKPU
Delay from RXC+/- active to data active
RXC+/- = 25MHz
100
µs
TPDL
Delay from PD/ PDO Low to high impedance outputs
8
ns
Notes:
1
Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
2
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
3
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
4
The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same
as the falling edge timing.
5 Measured when transmitter was powered down (see SiI/AN-0005 “PanelLink Basic Design /Application Guide,” Section 2.4).
6 Refer to the transmitter datasheet for minimum DE high and low time
7 Data is active (i.e. not tri-stated) but not valid yet. Data and controls are valid only when SCDT goes high. See T
FSC and
Figure 7.
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