PMC271 datasheet(4/90 Pages) PADAUK

4 / 90 page

PMC271/PMS271 Series

8-bit ADC FPPA

TM 8-bit Controller

Page 4 of 90

PDK-DS-PMX271-EN_V105 – Dec. 18, 2018

5.7.4. External Crystal Oscillator.........................................................................................38

5.7.5. System Clock and LVR levels ...................................................................................39

5.7.6. System Clock Switching............................................................................................40

5.8.

16-bit Timer (Timer16) ........................................................................................................41

5.9.

Watchdog Timer..................................................................................................................42

5.10.

Interrupt ..............................................................................................................................43

5.11.

Power-Save and Power-Down ............................................................................................45

5.11.1. Power-Save mode (“stopexe”) ................................................................................45

5.11.2. Power-Down mode (“stopsys”)................................................................................46

5.11.3. Wake-up .................................................................................................................47

5.12.

IO Pins ................................................................................................................................48

5.13.

Reset and LVR....................................................................................................................49

5.13.1. Reset ......................................................................................................................49

5.13.2. LVR reset................................................................................................................49

5.14.

LCD Half VDD Bias Voltage ................................................................................................49

5.15.

Analog-to-Digital Conversion (ADC) module .......................................................................50

5.15.1.The input requirement for AD conversion .................................................................52

5.15.2.ADC clock selection .................................................................................................52

5.15.3.AD conversion .........................................................................................................52

5.15.4.Configuring the analog pins .....................................................................................53

5.15.5.Using the ADC .........................................................................................................53

IO Registers....................................................................................................................... 54

6.1.

ACC Status Flag Register (flag), IO address = 0x00 ...........................................................54

6.2.

FPP unit Enable Register (fppen), IO address = 0x01 .........................................................54

6.3.

Stack Pointer Register (sp), IO address = 0x02...................................................................54

6.4.

Clock Mode Register (clkmd), IO address = 0x03 ...............................................................55

6.5.

Interrupt Enable Register (inten), IO address = 0x04...........................................................55

6.6.

Interrupt Request Register (intrq), IO address = 0x05 .........................................................55

6.7.

Timer 16 mode Register (t16m), IO address = 0x06............................................................56

6.8.

General Data register for IO (gdio), IO address = 0x07 .......................................................56

6.9.

External Oscillator setting Register (eoscr, write only), IO address = 0x0a..........................56

6.10.

IHRC oscillator control Register (ihrcr, write only), IO address = 0x0b ................................57

6.11.

Interrupt Edge Select Register (integs), IO address = 0x0c .................................................57

6.12.

Port A Digital Input Enable Register (padier), IO address = 0x0d ........................................58

6.13.

Port B Digital Input Enable Register (pbdier), IO address = 0x0e ........................................59

6.14.

Port A Data Registers (pa), IO address = 0x10 ...................................................................60

6.15.

Port A Control Registers (pac), IO address = 0x11..............................................................60

6.16.

Port A Pull-up Registers (paph), IO address = 0x12 ............................................................60

6.17.

Port B Data Registers (pb), IO address = 0x14 ...................................................................60

6.18.

Port B Control Registers (pbc), IO address = 0x15..............................................................60

6.19.

Port B Pull-up Registers (pbph), IO address = 0x16 ............................................................60

6.20.

ADC Control Register (adcc), IO address = 0x20 ................................................................60

6.21.

ADC Mode Register (adcm, write only), IO address = 0x21.................................................61

6.22.

ADC Result Register (adcr, read only), IO address = 0x22..................................................61

6.23.

ADC Reference High Control Register (adcrhc), IO address = 0x1c....................................61

6.24.

RESET Status Register (rstst), IO address = 0x25 ..............................................................62

6.25.

MISC Register (misc), IO address = 0x3b ...........................................................................62

Instructions ....................................................................................................................... 63

7.1.

Data Transfer Instructions ...................................................................................................64

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