2.1

User ID Location

A user may store identification information (User ID) in 32 designated locations. The User ID locations are mapped to

20 0000h-20 003Fh. Each location is 16 bits in length. Code protection has no effect on these memory locations.

Each location may be read with code protection enabled or disabled.

2.2

Device/Revision ID

The 16-bit Device ID Word is located at 3F FFFEh and the 16-bit Revision ID is located at 3F FFFCh. These

locations are read-only and cannot be erased or modified. See DEVICE ID and REVISION ID registers for more

details.

2.3

Device Configuration Information (DCI)

The Device Configuration Information (DCI) is a dedicated region in the memory that holds information about the

device which is useful for programming and bootloader applications. The data stored in this region is read-only and

cannot be modified/erased. Refer to the table below for complete DCI table addresses and description.

Table 2-1. DEVICE CONFIGURATION INFORMATION

Address

Name

Description

Value

Units

PIC18F04/14Q41

PIC18F05/15Q41

PIC18F06/16Q41

3C 0000h

ERSIZ

Erase Page Size

128

Words

3C 0002h

WLSIZ

Number of write

latches per row

0

Words

3C 0004h

URSIZ

Number of user

erasable pages

128

256

512

Pages

3C 0006h

EESIZ

Data EEPROM

memory size

1024

Bytes

3C 0008h

PCNT

Pin Count

Pins

Note: 

1.

Pin Count value of 14 is used for 16-pin parts as well.

2.4

Configuration Bytes

The devices have ten Configuration Bytes, starting at address, 30 0000h. Configuration bits enable or disable specific

features, placing these controls outside the normal software process, and they establish configured values prior to

the execution of any software.

In terms of programming, these important Configuration bits should be considered:

1.

LVP: Low-Voltage Programming Enable bit

bit is ignored.

It is important to note that the LVP bit cannot be written (to ‘0’) while operating from the LVP programming

interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming

from LVP mode, or accidentally eliminating LVP mode from the Configuration state. For more information, refer

to the Low-Voltage Programming (LVP) Mode section.

2.

MCLRE: Master Clear (MCLR) Enable bit

– If LVP = 1: RA3 pin function is MCLR

PIC18FXXQ41

Memory Map

Programming Specification

DS40002143B-page 7