47C16 datasheet(10/40 Pages) MICROCHIP

10 / 40 page

47L04/47C04/47L16/47C16

DS20005371C-page 10

 2015-2016 Microchip Technology Inc.

2.2

Device Addressing

The control byte is the first byte received following the

Start condition from the master device (Figure 2-3).

The control byte begins with a 4-bit operation code.

The next two bits are the user-configurable Chip

Select bits: A2 and A1. The next bit is a non-configu-

rable Chip Select bit that must always be set to ‘0’.

The Chip Select bits A2 and A1 in the control byte

must match the logic levels on the corresponding A2

and A1 pins for the device to respond.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’ a read operation is

selected, and when set to a ‘0’ a write operation is

selected.

The combination of the 4-bit operation code and the

three Chip Select bits is called the slave address.

Upon receiving a valid slave address, the slave device

outputs an acknowledge signal on the SDA line.

Depending on the state of the R/W bit, the 47XXX will

select a read or a write operation.

FIGURE 2-3:

CONTROL BYTE FORMAT

The 47XXX is divided into two functional units: the

SRAM array and the Control registers. Section 2.3

“SRAM Array”

describes the functionality for the

SRAM array and Section 2.4 “Control Registers”

describes the Control registers.

The 4-bit op code in the control byte determines which

unit will be accessed during an operation. Table 2-3

shows the standard control bytes used by the 47XXX.

Note:

When VCAP is below VTRIP, the 47XXX

cannot be accessed and will not

acknowledge any commands.

SACK

R/W

Op Code

Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

SACK

R/W

TABLE 2-3:

CONTROL BYTES

Operation

Code

Chip

Select

R/W

Bit

SRAM Read

1010

A2 A1 01

SRAM Write

1010

A2 A1 00

Control Register Read

0011

A2 A1 01

Control Register Write

0011

A2 A1 00

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