AD9166 datasheet(17/138 Pages) AD

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Data Sheet

AD9166

Rev. 0 | Page 17 of 138

Pin No.

Mnemonic

Description

RESET

Reset (Active Low) Input. CMOS levels on Pin M6 are

determined with respect to VDD_IO.

M13

CS_DAC

DAC Serial Port Chip Select (Active Low) Input. CMOS

levels on Pin M13 are determined with respect to

VDD_IO.

N6 to N14

DAC_1P2_DIG

1.2 V Digital Supply Voltage for the Digital Signal

Processing (DSP) Blocks of the DAC.

P1, R1

SERDIN6+, SERDIN6−

SERDES Lane 6 Negative and Positive Inputs.

P7, P15

DAC_3P3_SYNC

3.3 V SERDES Sync Supply Voltage.

P12, R12

SYNCOUT−,

SYNCOUT+

Negative and Positive LVDS Sync (Active Low) Output

Signals.

P18, R18

SERDIN1+, SERDIN1−

SERDES Lane 1 Positive and Negative Inputs.

R10

SERPLL_LDO_BYPASS

SERDES PLL Supply Voltage Bypass. Connect this pin with

a 1 Ω resistor in series with a 1 μF capacitor to ground.

V15, V14

SERDIN2+, SERDIN2−

SERDES Lane 2 Positive and Negative Inputs.

V12, V11

SERDIN3+, SERDIN3−

SERDES Lane 3 Positive and Negative Inputs.

V7, V8

SERDIN4+, SERDIN4−

SERDES Lane 4 Negative and Positive Inputs.

V4, V5

SERDIN5+, SERDIN5−

SERDES Lane 5 Negative and Positive Inputs.

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