5-3

FAST AND LS TTL DATA

SN54/74LS669

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

54

0.7

V

Guaranteed Input LOW Voltage for

VIL

Input LOW Voltage

74

0.8

V

pg

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65

– 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

54

2.5

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

VOH

Output HIGH Voltage

74

2.7

3.5

V

CC

, OH

,

IN

IH

or VIL per Truth Table

VOL

Output LOW Voltage

54, 74

0.25

0.4

V

IOL = 4.0 mA

VCC = VCC MIN,

VIN =VIL or VIH

VOL

Output LOW Voltage

74

0.35

0.5

V

IOL = 8.0 mA

VIN = VIL or VIH

per Truth Table

I

I

HIGH C

Others

20

µA

VCC = MAX VIN =2 7V

IIH

Input HIGH Current

Enable T

40

µA

VCC = MAX, VIN = 2.7 V

IIH

Input HIGH Current

Others

0.1

mA

VCC = MAX VIN =7 0V

Enable T

0.2

mA

VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

Others

–0.4

mA

VCC = MAX VIN =0 4V

IIL

Input LOW Current

Enable T

–0.8

mA

VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

–20

– 100

mA

VCC = MAX

ICC

Power Supply Current

34

mA

VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

25

32

MHz

C15 F

tPLH

tPHL

Propagation Delay,

Clock to RCO

26

40

40

60

ns

C15 F

tPLH

tPHL

Propagation Delay,

Clock to Any Q

18

18

27

27

ns

CL = 15 pF

tPLH

tPHL

Enable to RCO

11

29

17

45

ns

tPLH

tPHL

U/D to RCO

22

26

35

40

ns

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tW

Clock Pulse Width

20

ns

V5 0 V

ts

Data Setup Time

20

ns

V5 0 V

ts

Enable Setup Time

35

ns

VCC =5 0V

ts

Load Setup Time

25

ns

VCC = 5.0 V

ts

U/D Setup Time

30

ns

th

Hold Time, Any Input

0

ns