XRT75L03 datasheet(73/92 Pages) EXAR

73 / 92 page

XRT75L03

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR

REV. 1.0.4

TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03

Channel 1 Address Location = 0x0B

Channel 2 Address Location = 0x13

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Unused

Loss of PRBS

Pattern Sync

Digital LOS

Defect

Declared

Analog LOS

Defect

Declared

(FIFO Limit)

Alarm

Declared

Receive LOL

Defect

Declared

Receive LOS

Defect

Declared

Transmit

DMO

Condition

R/O

0000

000

BIT NUMBER

NAME

TYPE

DEFAULT

VALUE

DESCRIPTION

7Unused

R/O

Loss of PRBS Pat-

tern Lock

R/O

Loss of PRBS Pattern Lock Indicator:

This READ-ONLY bit-field indicates whether or not the

PRBS Receiver (within the Receive Section of Channel 0)

is declaring PRBS Lock within the incoming PRBS pattern.

If the PRBS Receiver detects a very large number of bit-

errors within its incoming data-stream, then it will declare

the Loss of PRBS Lock Condition.

Conversely, if the PRBS Receiver were to detect its pre-

determined PRBS pattern with the incoming DS3, E3 or

STS-1 data-stream, (with little or no bit errors) then the

PRBS Receiver will clear the Loss of PRBS Lock condition.

0 - Indicates that the PRBS Receiver is currently declaring

the PRBS Lock condition within the incoming DS3, E3 or

STS-1 data-stream.

1 - Indicates that the PRBS Receiver is currently declaring

the Loss of PRBS Lock condition within the incoming DS3,

E3 or STs-1 data-stream.

NOTE: This register bit is only valid if all of the following are

true.

a. The PRBS Generator block (within the Transmit

Section of the Chip is enabled).

b. The PRBS Receiver is enabled.

c. The PRBS Pattern (that is generated by the PRBS

Generator) is somehow looped back into the

Receive Path (via the Line-Side) and in-turn routed

to the receive input of the PRBS Receiver.

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