LM3075 datasheet(10/18 Pages) NSC

10 / 18 page

Operating Descriptions

GENERAL

The LM3075 solves the need within many portable systems

for 5V, 3.3V, 3.3V stand-by and 12V legacy power supplies.

The controller (IC) uses synchronous rectification and em-

ploys a peak current mode control scheme. Protection Fea-

tures include over-voltage protection (OVP), under-voltage

protection (UVP), thermal protection, and positive and nega-

tive peak current limiting. UVP functionality is automatically

disabled during soft-start and then enabled once the IC has

correctly started. The device operates with a wide input

voltage range from 4.5V to 36V.

SOFT START

In normal operation the soft-start functions as follows:

As the input voltage rises above the 4.2V UVLO threshold,

where the internal circuitry is powered on, an internal 2 µA

current starts to charge the capacitor connected between the

SS pin and ground. A minimum on-time comparator gener-

ates the soft-start PWM pulses. As the SS pin voltage ramps

up, the duty cycle increases, causing the output voltage to

ramp up. During this time, the error amplifier output voltage

is clamped at 2V, and the duty cycle generated by the PWM

comparator is ignored. When the output voltage exceeds

98.5% (typical) of the set target voltage, the regulator tran-

sitions from soft-start to operating mode. Beyond this point,

once the PWM pulses generated by the PWM comparator

are narrower than those generated by the minimum on-time

comparator, the PWM comparator takes over and starts to

regulate the output voltage. Peak current mode control now

takes place. The rate at which the duty cycle increases

depends on the capacitance of the soft-start capacitor. The

higher the capacitance, the slower the output voltage ramps

up.

A unique feature of the LM3075 is that the rate at which the

duty cycle grows is independent of the input voltage. This is

because the ramp signal used to generate the soft-start duty

cycle has a peak value proportional to the input voltage,

making the product of duty cycle and input voltage a con-

stant. This makes the soft-start process more predictable

and reliable.

During soft-start, under-voltage protection is temporarily sus-

pended but over-voltage protection and current limit remain

in effect. When the SS pin voltage exceeds 2V, a soft-start

time out signal is issued. This signal sets the under-voltage

protection into ready mode. This is discussed more in the

Under-Voltage Protection section.

If the SS pin is short-circuited to ground before startup, the

LM3075 operates at minimum duty cycle when it is enabled,

and the under-voltage protection is disabled.

FAULT STATE

When a fault condition is detected, a "fault" signal is gener-

ated internally. This signal discharges the capacitor con-

nected between the SS pin and ground with 4 µA of current

until the SS pin reaches 60mV. Once a level of 60mV is

reached at the SS pin, the IC restarts normally and resumes

operation assuming the cause of the fault condition has been

removed.

FORCE PWM MODE

Pulling the FPWM pin to logic low activates the force PWM

mode. In this mode, the top FET and the bottom FET gate

signals are always complementary to each other and the

Negative Current Limit comparator is activated (see Nega-

tive Current Limit section). In force PWM mode, the regulator

always operates in Continuous Conduction Mode (CCM) and

the duty cycle, which is approximately V

OUT/VIN

in this

mode, is almost independent of load. The force PWM mode

is good for applications where fixed switching frequency is

required. In forced PWM mode, the top FET has to be turned

on for a minimum of typically 180 ns each cycle. However, if

the required duty cycle is less than the minimum value, the

IC is unable to reach the desired voltage output in FPWM

mode. This causes the chip to enter a fault state and the IC

attempts to restart until the cause of the fault has been

removed (see the Fault State section).

SKIP COMPARATOR

Whenever the output voltage of the error amplifier (COMP

pin) goes below a 0.5V threshold, the PWM cycles are

"skipped" until that voltage exceeds the threshold again. Due

to the time required for the system loop to respond to

changes, it is unlikely that the system will oscillate around

the threshold and thus the system remains stable.

PULSE-SKIP MODE

Pulse-skip mode is activated by pulling the FPWM pin to a

TTL-compatible logic high. In this mode, the Zero-Crossing /

Negative Current Limit comparator detects the bottom FET

current. Once the bottom FET current flows from drain to

source, the bottom FET is turned off. This prevents negative

inductor current.

In force PWM operation, the inductor current is allowed to go

negative, so the regulator is always in Continuous Conduc-

tion Mode (CCM), no matter what the load is. In pulse-skip

mode, the regulator enters Discontinuous Conduction Mode

(DCM) under light loads. Once the regulator enters DCM, its

switching frequency drops as the load current decreases.

The minimum on-time comparator takes over causing the

output voltage to continuously rise and COMP pin voltage

(the error amplifier output voltage) to continuously drop.

When the COMP pin voltage hits the 0.5V level, the Cycle

Skip comparator toggles, causing the present switching

cycle to be "skipped", i.e., both FETs remain off during the

whole cycle. As long as the COMP pin voltage is below 0.5V,

no switching of the FETs happens. As a result, the output

voltage drops, and the COMP pin voltage rises. When the

COMP pin goes above the 0.5V level, the Cycle Skip com-

parator flips and allows a series of on-time pulses to happen.

If the load current is so small that this series of pulses is

enough to bring the output voltage up to such a level that the

COMP pin drops below 0.5V again, the pulse skipping hap-

pens again. Otherwise it may take a number of consecutive

pulses to bring the COMP pin voltage down to 0.5V again. As

the load current increases, it takes more and more consecu-

tive pulses to drive the COMP voltage to 0.5V. The pulse-

skipping stops when the load current is sufficiently high. In

pulse-skip mode, the frequency of the burst of switching

pulses varies directly with the load current. Since the load is

usually very light in pulse-skip mode, conducted noise is

very low and the variable operating frequency should cause

no EMI problems in the system.

The LM3075 pulse-skip mode helps the light load efficiency

for two reasons. First, the bottom FET is turned on only when

inductor current is in the positive conduction region, this

eliminates circulating energy loss. Second, the FETs switch

only when necessary, rather than every cycle, thus reducing

the FETs switching losses and gate drive power losses.

LM3075 Datasheet(PDF) 10 Page - National Semiconductor (TI)

LM3075 Datasheet(HTML) 10 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL