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AM29N323D Datasheet(PDF) 29 Page - Advanced Micro Devices |
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AM29N323D Datasheet(HTML) 29 Page - Advanced Micro Devices |
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29 / 48 page  28 Am29N323D August 8, 2002 AC CHARACTERISTICS Synchronous/Burst Read Notes: 1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from four cycles to seven cycles. 2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency is not present if PS is not enabled. 3. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. Figure 9. Burst Mode Read Parameter Description 11A (40 MHz) Unit JEDEC Standard tIACC Initial Access Time Max 120 ns tBACC Burst Access Time Valid Clock to Output Delay Max 20 ns tAVDS AVD# Setup Time to CLK Min 5 ns tAVDH AVD# Hold Time from CLK Min 7 ns tAVDO AVD# High to OE# Low Min 0 ns tACS Address Setup Time to CLK Min 5 ns tACH Address Hold Time from CLK Min 7 ns tBDH Data Hold Time from Next Clock Cycle Max 4 ns tOE Output Enable to Data, PS, or RDY Valid Max 20 ns tCEZ Chip Enable to High Z Max 10 ns tOEZ Output Enable to High Z Max 10 ns tCES CE# Setup Time to CLK Min 5 ns tRDYS RDY Setup Time to CLK Min 5 ns tRACC Ready access time from CLK Max 20 ns Da Da + 1 Da + 2 Da + n OE# A/DQ0: A/DQ15 A16: A20 Aa AVD# RDY CLK CE# tCES tAVDS tACS tAVDS tAVDO tACH tBACC tOE tRACC tRDYS tOEZ tCEZ tIACC tBDH Aa 5 cycles for initial access shown. Programmable wait state function is set to 01h. 1 cycle wait state when PS enabled 25 ns typ. Hi-Z Hi-Z Hi-Z |
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