LTC6930 datasheet(18/28 Pages) AD

18 / 28 page

LTC6994-1/LTC6994-2

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

Voltage-Controlled Delay

With one additional resistor, the LTC6994 output delay

can be manipulated by an external voltage. As shown in

Figure 10, voltage VCTRL sources/sinks a current through

RMOD to vary the ISET current, which in turn modulates

the delay as described in Equation (3):

tDELAY =

NDIV •RMOD

50kΩ

•

1µs

RMOD

RSET

–

VCTRL

VSET

(3)

Digital Delay Control

The control voltage can be generated by a DAC (digital-to-

analog converter), resulting in a digitally-controlled delay.

Many DACs allow for the use of an external reference. If

such a DAC is used to provide the VCTRL voltage, the VSET

dependency can be eliminated by buffering VSETandusing

it as the DAC’s reference voltage, as shown in Figure 11.

The DAC’s output voltage now tracks any VSET variation

and eliminates it as an error source. The SET pin cannot be

tied directly to the reference input of the DAC because the

currentdrawnbytheDAC’sREFinputwouldaffectthedelay.

ISET Extremes (Master Oscillator Frequency Extremes)

When operating with ISET outside of the recommended

1.25µA to 20µA range, the master oscillator operates

outside of the 62.5kHz to 1MHz range in which it is most

accurate.

The oscillator will still function with reduced accuracy for

ISET < 1.25µA. At approximately 500nA, the oscillator will

stop. Under this condition, the delay timing can still be

initiated, but will not terminate until ISET increases and

the master oscillator starts again.

At the other extreme, it is not recommended to operate

the master oscillator beyond 2MHz because the accuracy

of the DIV pin ADC will suffer.

LTC6994

GND

SET

OUT

V+

DIV

0.1µF

699412 F10

V+

RSET

RMOD

VCTRL

699412 F11

LTC6994

GND

SET

OUT

V+

DIV

0.1µF

V+

RMOD

RSET

–

V+

1/2

LTC6078

LTC1659

V+

0.1µF

VCC

REF

GND

VOUT

µP

DIN

CLK

CS/LD

NDIV • RMOD

50k

tDELAY =

DIN = 0 TO 4095

•

–

RMOD

RSET

DIN

4096

1µs

0.1µF

Figure 10. Voltage-Controlled Delay

Figure 11. Digitally Controlled Delay

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