ISO6721 datasheet(18/48 Pages) TI

18 / 48 page

8.3 Feature Description

The ISO672x-Q1 family of devices is available in two channel configurations and default output state options to

enable a variety of application uses. Table 8-1 lists the device features of the ISO672x-Q1 devices.

Table 8-1. Device Features

PART NUMBER

MAXIMUM DATA

RATE

CHANNEL DIRECTION

DEFAULT OUTPUT

STATE

PACKAGE

RATED ISOLATION(1)

ISO6720-Q1

50 Mbps

2 Forward, 0 Reverse

High

DWV-8

5000 VRMS / 7071 VPK

ISO6720F-Q1

50 Mbps

2 Forward, 0 Reverse

Low

DWV-8

5000 VRMS / 7071 VPK

ISO6721-Q1

50 Mbps

1 Forward, 1 Reverse

High

DWV-8

5000 VRMS / 7071 VPK

ISO6721B-Q1

50 Mbps

1 Forward, 1 Reverse

High

D-8

3000 VRMS / 4242 VPK

ISO6721F-Q1

50 Mbps

1 Forward, 1 Reverse

Low

DWV-8

5000 VRMS / 7071 VPK

ISO6721FB-Q1

50 Mbps

1 Forward, 1 Reverse

Low

D-8

3000 VRMS / 4242 VPK

(1)

See Section 6.8 for detailed isolation ratings.

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 25 . Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO672x-

Q1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of

these improvements include:

• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

• Low-resistance connectivity of ESD cells to supply and ground pins.

• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

ISO6720-Q1, ISO6721-Q1

SLLSFF5A – JULY 2020 – REVISED DECEMBER 2020

www.ti.com

Submit Document Feedback

Product Folder Links: ISO6720-Q1 ISO6721-Q1

ISO6721 Datasheet(PDF) 18 Page - Texas Instruments

ISO6721 Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL