RA4M3 datasheet(3/92 Pages) RENESAS

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Table 1.3

System (2 of 2)

Functional description

Clocks

● Main clock oscillator (MOSC)

● Sub-clock oscillator (SOSC)

● High-speed on-chip oscillator (HOCO)

● Middle-speed on-chip oscillator (MOCO)

● Low-speed on-chip oscillator (LOCO)

● IWDT-dedicated on-chip oscillator

● PLL/PLL2

● Clock out support

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock selected as the

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.When measurement is

complete or the number of pulses within the time generated by the measurement reference clock

is not within the allowable range, an interrupt request is generated.

Interrupt Controller Unit (ICU)

The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector

Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)

modules. The ICU also controls non-maskable interrupts.

Low power modes

Power consumption can be reduced in multiple ways, including setting clock dividers, stopping

modules, selecting power control mode in normal operation, and transitioning to low power

modes.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery-powered area

includes the RTC, SOSC, backup memory, and switch between VCC and VBATT.

The register write protection function protects important registers from being overwritten due to

software errors. The registers to be protected are set with the Protect Register (PRCR).

Memory Protection Unit (MPU)

The MCU has one Memory Protection Unit (MPU).

Table 1.4

Event link

Feature

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the event requests generated by various peripheral

modules as source signals to connect them to different modules, allowing direct link between the

modules without CPU intervention.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request.

DMA Controller (DMAC)

The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data

without intervention from the CPU. When a DMA transfer request is generated, the DMAC

transfers data stored at the transfer source address to the transfer destination address.

Table 1.6

External bus interface

Feature

Functional description

External buses

● QSPI area (EQBIU): Connected to the QSPI (external device interface)

Table 1.7

Timers (1 of 2)

Feature

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with

GPT16 × 4 channels. PWM waveforms can be generated by controlling the up-counter, down-

counter, or the up- and down-counter. In addition, PWM waveforms can be generated for

controlling brushless DC motors. The GPT can also be used as a general-purpose timer.

Port Output Enable for GPT (POEG)

The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins

in the output disable state

RA4M3 Datasheet

1. Overview

R01DS0368EJ0120 Rev.1.20

Dec 2, 2020

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