A6986H3V3 datasheet(20/71 Pages) STMICROELECTRONICS

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5.3.2

Output voltage sequencing

The A6986H device implements sequencing connecting the RST pin of the master device to the SS/INH of the

slave. The slave is inhibited as long as the master output voltage is outside regulation so implementing the

sequencing, see Figure 12. Output voltage sequencing.

Figure 12. Output voltage sequencing

VOUT3

VOUT2

VOUT1

tDELAY1

tDELAY2

tDELAY3

High flexibility is achieved thanks to the programmable RST thresholds (Table 7. LNM/ LCM selection

(A6986H3V3) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. and Table 8. LNM/ LCM selection

(A6986H5V) TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.) and programmable delay time. To

minimize the component count the DELAY pin capacitor can be also omitted so the pin works as a normal Power

Good.

5.4

Error amplifier

The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose

non inverting input is connected to the internal voltage reference (0.85 V), while the inverting input (FB) is

connected to the external divider or directly to the output voltage.

Table 10. Uncompensated error amplifier characteristics

Description

Value

Transconductance

155 µS

Low frequency gain

100 dB

The error amplifier output is compared with the inductor current sense information to perform PWM control. The

error amplifier also determines the burst operation at light-load when the LCM is active.

5.5

Output voltage line regulation

The regulator features an enhanced line regulation thanks to the peak current mode architecture. Figure 13. VOUT

= 3.3 V line regulation shows negligible output voltage variation (normalized to the value measured at VIN = 12 V)

over the entire input voltage range for the A6986H with VOUT = 3.3V.

A6986H

Error amplifier

DS12861 - Rev 3

page 20/71

A6986H3V3 Datasheet(PDF) 20 Page - STMicroelectronics