Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

STM32L552CC Datasheet(PDF) 31 Page - STMicroelectronics

Part # STM32L552CC
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU, 165 DMIPS, up to 512 KB Flash memory, 256 KB SRAM, SMPS
PDF  340 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L552CC Datasheet(HTML) 31 Page - STMicroelectronics

Back Button STM32L552CC_V01 Datasheet HTML 27Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 28Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 29Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 30Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 31Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 32Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 33Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 34Page - STMicroelectronics STM32L552CC_V01 Datasheet HTML 35Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 31 / 340 page
background image
DS12737 Rev 6
31/340
STM32L552xx
Functional overview
78
Default TrustZone security state
The default system security state is:
•
CPU:
–Cortex®-M33 is in secure state after reset. The boot address must be in secure
address.
•
Memory map:
–
SAU: is fully secure after reset. Consequently, all memory map is fully secure. Up
to 8 SAU configurable regions are available for security attribution.
•
Flash:
–
Flash security area is defined by watermark user options.
–
Flash block based area is non-secure after reset.
•
SRAMs:
–
All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
•
External memories:
–
FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) are secure
•
Peripherals
–
Securable peripherals are non-secure after reset.
–
TrustZone-aware peripherals (except the GPIO) are non-secure after reset. Their
secure configuration registers are secure.
Note:
Refer to Table 7 and Table 8 for a list of Securable and TrustZone-aware peripherals.
•
All GPIO are secure after reset.
•
Interrupts:
–
NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-
secure state.
–
TZIC: All illegal access interrupts are disabled after reset.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com